The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
A prefetch circuit may generate prefetch requests for information that may subsequently be required by a processor. The prefetch circuit may improve processor performance by reducing memory latency. However, when prefetched information is not subsequently required by the processor, such prefetching may lead to performance degradation and polluting the local cache.
The prefetch circuit may predict prefetch information addresses based on previously requested addresses. In particular, the prefetch circuit may use prior patterns of accessing memory addresses to predict a next address for prefetching from that memory.
The prefetch circuit may prefetch computer programming instructions for execution by the processor, data to be used in operations performed by the processor, or both.
A data structure used to organize the data may produce access patterns that, when recognized by the prefetch circuit, may improve the reliability of a predicted address for prefetching the data. The data structure may be a multi-dimensional matrix.